Q:

Conversion of RTL description to Boolean _______ description is a function of the translation procedure in the synthesis process.

A) Optimized B) Unoptimized
C) Translation D) PLA format
 
Answer & Explanation Answer: B) Unoptimized

Explanation: Conversion of RTL description to Boolean unoptimized description is a function of translation procedure in the synthesis process. The logic synthesis tool converts the description to an unoptimized, intermediate, internal representation.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

7
Q:

Simulator enters in which phase after the initialization phase?

A) Execution phase B) Compilation phase
C) Elaboration phase D) Simulation phase
 
Answer & Explanation Answer: A) Execution phase

Explanation: Simulator enters in execution phase after the initialization phase, the actual simulation of the behaviour of the design takes place in the execution phase. Each simulation process in the active queue is taken out and executed until it suspends.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

6
Q:

Hold time is the time needed for the data to ________ after the edge of the clock is triggered.

A) Decrease B) Increase
C) Remain constant D) Negate
 
Answer & Explanation Answer: C) Remain constant

Explanation: Hold time is the time needed for the data to remain constant after the edge of the clock is triggered. Data must remain stable, if the incorrect data is latched then, it leads to hold violation.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

8
Q:

Setup time is the time required for input data to settle after the triggering edge of the clock.

A) True B) False
 
Answer & Explanation Answer: B) False

Explanation: The time required for an input data to settle BEFORE the triggering edge of the clock is called the setup time. It is measured with respect to active clock pulse edge only.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

9
Q:

RTL is a combination of both combinational and sequential circuits.

A) True B) False
 
Answer & Explanation Answer: A) True

Explanation: RTL is a combination of both combinational and sequential circuits. Combinational logic performs all the logical operations in the circuit and it typically consists of basic logic gates and registers make synchronized sequential logic.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

7
Q:

Which of the following tool performs logic optimization?

A) Simulation tool B) Synthesis tool
C) Routing tool D) RTL compiler
 
Answer & Explanation Answer: B) Synthesis tool

Explanation: Synthesis tool performs logic optimization in RTL by converting high-level description of the design circuit into an optimized gate level representation by the use of basic logic gates like and, or, nor, etc.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

10
Q:

Which flip-flop is usually used in the implementation of the registers?

A) D flip-flop B) S-R flip-flop
C) T flip-flop D) J-K flip-flop
 
Answer & Explanation Answer: A) D flip-flop

Explanation: Registers are generally implemented as D flip-flops because connection for the shift register is the simplest with D flip-flop, as there is a single data input in it. The flip-flop also stores the output of whatever logic is applied to its data input as long as the clock input is high.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

10
Q:

RTL mainly focuses on describing the flow of signals between ________

A) Logic gates B) Registers
C) Clock D) Inverter
 
Answer & Explanation Answer: B) Registers

Explanation: RTL focuses on describing the flow of signals between registers. There is a regularly repeated path of logic from the output of the register to its input, that is the reason it is called register transfer level.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

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