0
Q:

The operator ‘&’ is called the_____ operator.

A) Logical AND operator B) Bitwise AND operator
C) Arithmetic addition operator D) Concatenation operator
 
Answer & Explanation Answer: D) Concatenation operator

Explanation: ‘&’ is called the concatenation operator and is a binary operator. It needs two operands and both of them must be arrays. It combines two arrays and produces one array of the size equal to the sum of sizes of two arrays.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

1642
Q:

A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?

A) 20 ns B) 30 ns
C) 40 ns D) Output will remain zero
 
Answer & Explanation Answer: B) 30 ns

Explanation: In case of transport delay model, all the spikes and pulses, no matter how small, are taken into consideration i.e. not swallowed down. Transport delay order the events rather than just scheduling the last event. Therefore, when the buffer is executed at 10 ns, it will schedule a 1 at B at 30 ns. After which, it is again executed at 20 ns and hence the output will be zero again at 40 ns.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

1462
Q:

Complete description of the circuit to be designed is given in _________

A) Architecture B) Entity
C) Library D) Configurations
 
Answer & Explanation Answer: A) Architecture

Explanation: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

460
Q:

For any concurrent assignment statement, which of the following is true?

A) The statement is executed once B) The statement is executed twice
C) The value of left operand is assigned to right operand D) The statement is executed as many times as the value changes
 
Answer & Explanation Answer: D) The statement is executed as many times as the value changes

Explanation: A concurrent assignment statement assigns the value of right operand to left operand and this statement is executed many times. Whenever the value of right operand is changed, the assignment statement is executed.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

426
Q:

A package is designed called mux4to1_package, in which a component called mux4to1 is defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using the same component only, how many times he needs to use the PORT MAP statement?

A) 2 B) 3
C) 4 D) 5
 
Answer & Explanation Answer: D) 5

Explanation: The problem statement says that a 16:1 MUX is to be designed by using 4:1 multiplexers only. This can be done by using 5 numbers of 4 to 1 multiplexers. Here, 4 MUXs are required to collect all the inputs and one is used to select one from the 4 multiplexers outputs.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

400
Q:

A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the inertial delay model is used?

A) 30 ns B) 40 ns
C) 20 ns D) Output will remain zero
 
Answer & Explanation Answer: D) Output will remain zero

Explanation: Inertial delay model swallows the pulses or spikes in between the delay time period. The buffer is executed at 0 ns for the delay of 20 ns and then the value of A changes at 10 ns, which again execute buffer and schedule the output to be 1 at 30 ns. But at 20 ns, the value of A again changes which executes the buffer again and schedule the output to be zero at 40 ns. Therefore, the output will not change. Inertial model doesn’t order events it will take into consideration only the last event.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

399
Q:

Which of the following statement is used in structural modeling?

A) portmap() B) process()
C) if-else D) case
 
Answer & Explanation Answer: A) portmap()

Explanation: In structural modeling, the graphical representation of the system is described. All the modules, instances or components are defined along with their interconnections. It is defined that how the components are connected to each other by using nets or wires. The portmap() function is used to map the specific component in the design.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

399
Q:

How many logical operations are required to implement a Boolean function XY + X?

A) 0 B) 1
C) 2 D) 3
 
Answer & Explanation Answer: A) 0

Explanation: The given function XY + X is first optimized to reduce the cost of implementation. So, the optimized function will be equal to X. As XY + X = X (Y + 1) = X. To implement this no logical operation is needed. It just needs an assignment statement and no operation.

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Category: Electronics & Electrical MCQs
Sub Category: VHDL Mcqs

370